The present invention relates to a circuits for receiving clock signals and for latching command signals, and more particularly to a circuit configured to function as a receiver and a latch at the same time.
High speed electronic systems often have critical timing requirements. In semiconductor memory devices, such as DRAM, SDRAM, DDR-SDRAM and the like, external clock and command signals are received by receivers within the memory device. These internal receivers then generate corresponding internal clock and command signals that are synchronized appropriately. In many applications, the internally generated clock signals have propagation delays that must be matched in the internally generated command signals in order to maintain proper synchronization.
For these and other reasons the need exits for the present invention.